A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST
نویسندگان
چکیده
This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS’89 benchmark circuits. key words: low power BIST (Built-in Self Test), pseudo-random BIST, low power pattern generator
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 91-D شماره
صفحات -
تاریخ انتشار 2008